In some applications, the power supply current of an electronic circuit which is available to operate a processing circuit (e.g. of a synchronous digital device) is variable and may be insufficient to operate the processing circuit at the maximal clock frequency that is supported by the electronic circuit. This issue may be addressed by controlling the clock generation for the processing circuit in order to prevent the power supply voltage to drop under a minimal allowed value. Approaches for an efficient clock regulation that allows high performance with respect to the available current are desirable.